Capacitive micromachined ultrasonic transducers (CMUTs) have become an attractive candidate for next-generation ultrasonic imaging and therapy systems. Currently, CMUTs are fabricated using standard micromachining techniques, which facilitate realization of densely populated transducer arrays with a broad operating frequency range and various array configurations. The efficiency of this electrostatic transducer mainly depends on the ability to maintain an electric field in the gap with the strength on the order of 108 V/cm, or higher. For that reason, microfabrication technology has been the principal enabler for CMUTs.
The two main fabrication approaches used for CMUTs are sacrificial release and wafer bonding processes. The sacrificial release method is based on the basic principle of forming a cavity underneath a thin plate by first depositing and patterning a sacrificial layer on the substrate followed by the deposition of the plate layer and then selectively removing the sacrificial layer with a wet chemical etchant. The wet etchant in this process is introduced through holes opened between the cells to reach the sacrificial layer under the plate material. As this is a wet chemical process, the cavities must be dried after the removal of the sacrificial material. Drying the cavities is a critical step, which can lead to collapse of the structure due to capillary forces, a phenomenon referred to as stiction. In the sacrificial release process, the insulation layer, sacrificial layer, and thin plate are usually formed using chemical vapor deposition (CVD), and hence the control over the layer thickness, uniformity, and stress is not very precise. The plate thickness is limited by the CVD process, which makes it difficult to achieve CMUTs with thick plates. In sacrificially released CMUTs, the low-resistivity silicon substrate often serves as the bottom electrode resulting in overlap of top and bottom electrodes in the post area between active cells. This overlap increases the parasitic capacitance and can adversely affect the dielectric reliability of the device. Another shortcoming of the sacrificial release process is that the fill factor is limited due to the inactive region between cells that is used for sealing. Achieving high fill factor is especially critical to realize broadband operation at high frequencies.
The other main fabrication method for CMUTs is based on wafer bonding. This approach simplifies the fabrication by transferring a plate with precise mechanical properties over predefined cavities with a single bonding step. The basic process flow in this approach is as follows. A conductive silicon substrate is first thermally oxidized. The resulting silicon dioxide layer is patterned and etched down to the silicon substrate to define the active region of the transducer. A second thermal oxidation is used to grow the insulating layer on the bottom surface of the active region. A silicon-on-insulator (SOI) wafer is fusion-bonded on the processed wafer in vacuum. The wafers are annealed at high temperature (i.e., 1100° C.), to form strong covalent bonds. The handle portion and the buried oxide (BOX) layer of the SOI wafer are removed to realize a thin single-crystal silicon plate suspended over the cavities. Individual elements are defined by etching isolation trenches in the silicon plate. The major advantage of the wafer bonding approach is the improved control over the thickness, uniformity, and mechanical properties of the vibrating plate, thanks to the single-crystal silicon device layer of the SOI wafer. The fill factor is improved by eliminating the dead space between cells. In this process, dielectric reliability and parasitic capacitance continue to be issues as the dielectric post structure cannot be made thick if a thin gap is desired for good electromechanical efficiency. In a variant of this process, an extended insulation layer structure is formed in the post area by local oxidation of silicon (LOCOS) to address the low breakdown voltage and high parasitic capacitance issues associated with the described basic wafer bonding process. In this approach, because the LOCOS process also results in lateral oxide growth, the thickness and width of the post structure are coupled, which could be a limitation to implement high-frequency arrays with high fill factor. Other approaches such as using a thick BOX layer to form completely insulated silicon bottom electrodes below the active plate region in each CMUT cell are proposed. All of these approaches introduce additional complexities in the fabrication process and result in increased cost and degradation of the yield.
In the summarized conventional CMUT structures, usually, a low-resistivity silicon substrate is used as the bottom electrode. The parasitic capacitance is mainly caused by the overlap of the substrate and the top electrode in the post region. It has been previously shown that a patterned metal bottom electrode on a quartz substrate results in reduced parasitic capacitance. However, this process, being based on sacrificial release, suffers from poorer control over thickness, uniformity, and stress of deposited layers compared with wafer-bonding-based approaches.
Anodic bonding comes across as an appealing way of combining the benefits of wafer bonding and an insulating substrate. One can define a patterned metal bottom electrode on cavities etched in a glass substrate and anodically bond a silicon or SOI wafer on top to realize a CMUT. However, one major shortcoming of previously demonstrated anodically bonded CMUTs is the lack of vacuum cavity due to outgassing during bonding. In these devices, either the cavities were pressurized with the trapped oxygen gas under a thick plate or the cavities were exposed to the outside, making the transducer unsuited for immersion operation.
A CMUT having an anodically bonded plate and an air-tight, vacuum sealed cavity and methods of fabricating same are therefore desired to fill this gap.